The random access memory (RAM) commonly used in an asynchronous FIFO includes dual port random access memories and single port random access memories. Generally speaking, the structure of a dual port RAM provides faster access speed, but the chip size for the structure is bigger. While the access speed of a single port RAM is slower, the chip size is smaller. FIG. 1 illustrates a conventional asynchronous FIFO consisting of single port RAM banks, input FIFO ports and output FIFO ports.
For designing an asynchronous dual port FIFO, a circuit structure with a "metastable" architecture can be used to synchronize the accessing control signal if the data in the FIFO are accessed one by one. The main circuit in a metastable architecture comprises three D-type flip-flops and is well known to a person skilled in the field. However, in the case of a write frequency f.sub.1 and a read frequency f.sub.2, a typical metastable architecture can not be used when burst accessing mode is applied in the asynchronous FIFO design if 0.5f.sub.2 &lt;f.sub.1 &lt;f.sub.2 or 0.5f.sub.1 &lt;f.sub.2 &lt;f.sub.1.
Basically, the problem of controlling an asynchronous FIFO is that in an asynchronous FIFO, different access frequencies may result in uncertainty of addresses specified by the read pointer and the write pointer. It is thus hard to determine if the current FIFO status is full or empty.
FIG. 2 illustrates an asynchronous dual port FIFO in which the Gray code method is used to design the FIFO. The architecture of FIG. 2 represents one of the most common approaches to solving the problem associated with the unstable memory addresses. This structure reduces the number of bits of an unstable transient state in a read pointer or write pointer to the minimum, while the pointers are being sampled.
In the design of FIG. 2, the asynchronous FIFO comprises two Gray code counters. One is used as a read pointer, and the other is used as a write pointer. To determine how much memory space in the FIFO memory can be accessed, the Gray codes corresponding to the read and write pointers are first converted to sequential counts. A subtraction is then performed on the two sequential counts in order to determine the available space in the FIFO.
However, the design in FIG. 2 has some disadvantages. Because of different access frequencies to an asynchronous FIFO, the relative positions between these two pointers may not actually tell the true use level of the FIFO even with a synchronized circuit implementation. It also requires two status indicator circuits to determine whether the current FIFO status is full or empty.